MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part NumberATMEGA16A-PU
DescriptionMCU AVR 16K FLASH 16MHZ 40-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA16A-PU datasheets
 


Specifications of ATMEGA16A-PU

Core ProcessorAVRCore Size8-Bit
Speed16MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o32
Program Memory Size16KB (8K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case40-DIP (0.600", 15.24mm)Processor SeriesATMEGA16x
CoreAVR8Data Bus Width8 bit
Data Ram Size1 KBInterface Type2-Wire/SPI/USART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os32
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitPackage40PDIP
Device CoreAVRFamily NameATmega
Maximum Speed16 MHzOperating Supply Voltage3.3|5 V
Controller Family/seriesAVR MEGANo. Of I/o's32
Eeprom Memory Size512ByteRam Memory Size1KB
Cpu Speed16MHzRohs CompliantYes
For Use WithATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KITLead Free Status / RoHS StatusLead free / RoHS Compliant
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• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC.
These bits also select the gain for the differential channels. See
bits are changed during a conversion, the change will not go in effect until this conversion is
complete (ADIF in ADCSRA is set).
Table 22-4.
MUX4:0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
(1)
01010
(1)
01011
01100
01101
(1)
01110
(1)
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
ATmega16A
222
Input Channel and Gain Selections
Single Ended
Positive Differential
Input
Input
ADC0
ADC1
ADC2
ADC3
N/A
ADC4
ADC5
ADC6
ADC7
ADC0
ADC1
ADC0
ADC1
ADC2
ADC3
ADC2
ADC3
ADC0
ADC1
N/A
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC0
ADC1
ADC2
ADC3
ADC4
Table 22-4
for details. If these
Negative Differential Input
Gain
ADC0
10x
ADC0
10x
ADC0
200x
ADC0
200x
ADC2
10x
ADC2
10x
ADC2
200x
ADC2
200x
ADC1
1x
ADC1
1x
ADC1
1x
ADC1
1x
ADC1
1x
ADC1
1x
ADC1
1x
ADC1
1x
ADC2
1x
ADC2
1x
ADC2
1x
ADC2
1x
ADC2
1x
8154B–AVR–07/09