MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part NumberATMEGA16A-PU
DescriptionMCU AVR 16K FLASH 16MHZ 40-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA16A-PU datasheets
 


Specifications of ATMEGA16A-PU

Core ProcessorAVRCore Size8-Bit
Speed16MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o32
Program Memory Size16KB (8K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case40-DIP (0.600", 15.24mm)Processor SeriesATMEGA16x
CoreAVR8Data Bus Width8 bit
Data Ram Size1 KBInterface Type2-Wire/SPI/USART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os32
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitPackage40PDIP
Device CoreAVRFamily NameATmega
Maximum Speed16 MHzOperating Supply Voltage3.3|5 V
Controller Family/seriesAVR MEGANo. Of I/o's32
Eeprom Memory Size512ByteRam Memory Size1KB
Cpu Speed16MHzRohs CompliantYes
For Use WithATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KITLead Free Status / RoHS StatusLead free / RoHS Compliant
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Page 229/352

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The TMS input must be held low during input of the 3 LSBs in order to remain in the Shift-IR
state. The MSB of the instruction is shifted in when this state is left by setting TMS high.
While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out on
the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI
and TDO and controls the circuitry surrounding the selected Data Register.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched
onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR,
Pause-IR, and Exit2-IR states are only used for navigating the state machine.
• At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift
Data Register – Shift-DR state. While in this state, upload the selected Data Register
(selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input
at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be
held low during input of all bits except the MSB. The MSB of the data is shifted in when this
state is left by setting TMS high. While the Data Register is shifted in from the TDI pin, the
parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the
TDO pin.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data
Register has a latched parallel-output, the latching takes place in the Update-DR state. The
Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine.
As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting
JTAG instruction and using Data Registers, and some JTAG instructions may select certain
functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state.
Note:
For detailed information on the JTAG specification, refer to the literature listed in
on page
23.5
Using the Boundary-scan Chain
A complete description of the Boundary-scan capabilities are given in the section
(JTAG) Boundary-scan” on page
23.6
Using the On-chip Debug System
As shown in
• A scan chain on the interface between the internal AVR CPU and the internal peripheral units
• Break Point unit
• Communication interface between the CPU and JTAG system
All read or modify/write operations needed for implementing the Debugger are done by applying
AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O
memory mapped location which is part of the communication interface between the CPU and the
JTAG system.
The Break Point Unit implements Break on Change of Program Flow, Single Step Break, 2 Pro-
gram Memory Break Points, and 2 combined Break Points. Together, the 4 Break Points can be
configured as either:
• 4 single Program Memory Break Points
• 3 Single Program Memory Break Point + 1 single Data Memory Break Point
8154B–AVR–07/09
Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be
entered by holding TMS high for five TCK clock periods.
231.
232.
Figure
23-1, the hardware support for On-chip Debugging consists mainly of:
ATmega16A
“Bibliography”
“IEEE 1149.1
229