MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part NumberATMEGA16A-PU
DescriptionMCU AVR 16K FLASH 16MHZ 40-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA16A-PU datasheets
 


Specifications of ATMEGA16A-PU

Core ProcessorAVRCore Size8-Bit
Speed16MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o32
Program Memory Size16KB (8K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case40-DIP (0.600", 15.24mm)Processor SeriesATMEGA16x
CoreAVR8Data Bus Width8 bit
Data Ram Size1 KBInterface Type2-Wire/SPI/USART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os32
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitPackage40PDIP
Device CoreAVRFamily NameATmega
Maximum Speed16 MHzOperating Supply Voltage3.3|5 V
Controller Family/seriesAVR MEGANo. Of I/o's32
Eeprom Memory Size512ByteRam Memory Size1KB
Cpu Speed16MHzRohs CompliantYes
For Use WithATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KITLead Free Status / RoHS StatusLead free / RoHS Compliant
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Page 38/352

Download datasheet (8Mb)Embed
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Figure 10-1. Reset Logic
10.1.2
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in
V
is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as
CC
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
when V
CC
Figure 10-2. MCU Start-up, RESET Tied to V
ATmega16A
38
Power-on
Reset Circuit
Brown-out
BODEN
Reset Circuit
BODLEVEL
Pull-up Resistor
SPIKE
Reset Circuit
FILTER
JTAG Reset
Watchdog
Register
Timer
Watchdog
Oscillator
Clock
Generator
CKSEL[3:0]
SUT[1:0]
“System and Reset Characteristics” on page
rise. The RESET signal is activated again, without any delay,
CC
decreases below the detection level.
V
POT
V
CC
V
RST
RESET
t
TOUT
TIME-OUT
INTERNAL
RESET
DATA BUS
MCU Control and Status
Register (MCUCSR)
Delay Counters
CK
TIMEOUT
296. The POR is activated whenever
.
CC
8154B–AVR–07/09