MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part NumberATMEGA16A-PU
DescriptionMCU AVR 16K FLASH 16MHZ 40-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA16A-PU datasheets
 


Specifications of ATMEGA16A-PU

Core ProcessorAVRCore Size8-Bit
Speed16MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o32
Program Memory Size16KB (8K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case40-DIP (0.600", 15.24mm)Processor SeriesATMEGA16x
CoreAVR8Data Bus Width8 bit
Data Ram Size1 KBInterface Type2-Wire/SPI/USART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os32
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitPackage40PDIP
Device CoreAVRFamily NameATmega
Maximum Speed16 MHzOperating Supply Voltage3.3|5 V
Controller Family/seriesAVR MEGANo. Of I/o's32
Eeprom Memory Size512ByteRam Memory Size1KB
Cpu Speed16MHzRohs CompliantYes
For Use WithATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KITLead Free Status / RoHS StatusLead free / RoHS Compliant
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30. Instruction Set Summary
Mnemonics
Operands
Description
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
ADC
Rd, Rr
Add with Carry two Registers
ADIW
Rdl,K
Add Immediate to Word
SUB
Rd, Rr
Subtract two Registers
SUBI
Rd, K
Subtract Constant from Register
SBC
Rd, Rr
Subtract with Carry two Registers
SBCI
Rd, K
Subtract with Carry Constant from Reg.
SBIW
Rdl,K
Subtract Immediate from Word
AND
Rd, Rr
Logical AND Registers
ANDI
Rd, K
Logical AND Register and Constant
OR
Rd, Rr
Logical OR Registers
ORI
Rd, K
Logical OR Register and Constant
EOR
Rd, Rr
Exclusive OR Registers
COM
Rd
One’s Complement
NEG
Rd
Two’s Complement
SBR
Rd,K
Set Bit(s) in Register
CBR
Rd,K
Clear Bit(s) in Register
INC
Rd
Increment
DEC
Rd
Decrement
TST
Rd
Test for Zero or Minus
CLR
Rd
Clear Register
SER
Rd
Set Register
MUL
Rd, Rr
Multiply Unsigned
MULS
Rd, Rr
Multiply Signed
MULSU
Rd, Rr
Multiply Signed with Unsigned
FMUL
Rd, Rr
Fractional Multiply Unsigned
FMULS
Rd, Rr
Fractional Multiply Signed
FMULSU
Rd, Rr
Fractional Multiply Signed with Unsigned
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
IJMP
Indirect Jump to (Z)
JMP
k
Direct Jump
RCALL
k
Relative Subroutine Call
ICALL
Indirect Call to (Z)
CALL
k
Direct Subroutine Call
RET
Subroutine Return
RETI
Interrupt Return
CPSE
Rd,Rr
Compare, Skip if Equal
CP
Rd,Rr
Compare
CPC
Rd,Rr
Compare with Carry
CPI
Rd,K
Compare Register with Immediate
SBRC
Rr, b
Skip if Bit in Register Cleared
SBRS
Rr, b
Skip if Bit in Register is Set
SBIC
P, b
Skip if Bit in I/O Register Cleared
SBIS
P, b
Skip if Bit in I/O Register is Set
BRBS
s, k
Branch if Status Flag Set
BRBC
s, k
Branch if Status Flag Cleared
BREQ
k
Branch if Equal
BRNE
k
Branch if Not Equal
BRCS
k
Branch if Carry Set
BRCC
k
Branch if Carry Cleared
BRSH
k
Branch if Same or Higher
BRLO
k
Branch if Lower
BRMI
k
Branch if Minus
BRPL
k
Branch if Plus
BRGE
k
Branch if Greater or Equal, Signed
BRLT
k
Branch if Less Than Zero, Signed
BRHS
k
Branch if Half Carry Flag Set
BRHC
k
Branch if Half Carry Flag Cleared
BRTS
k
Branch if T Flag Set
ATmega16A
336
Flags
Operation
Rd ← Rd + Rr
Z,C,N,V,H
Rd ← Rd + Rr + C
Z,C,N,V,H
Rdh:Rdl ← Rdh:Rdl + K
Z,C,N,V,S
Rd ← Rd - Rr
Z,C,N,V,H
Rd ← Rd - K
Z,C,N,V,H
Rd ← Rd - Rr - C
Z,C,N,V,H
Rd ← Rd - K - C
Z,C,N,V,H
Rdh:Rdl ← Rdh:Rdl - K
Z,C,N,V,S
Rd ← Rd • Rr
Z,N,V
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
Rd ← Rd v K
Z,N,V
Rd ← Rd ⊕ Rr
Z,N,V
Rd ← $FF − Rd
Z,C,N,V
Rd ← $00 − Rd
Z,C,N,V,H
Rd ← Rd v K
Z,N,V
Rd ← Rd • ($FF - K)
Z,N,V
Rd ← Rd + 1
Z,N,V
Rd ← Rd − 1
Z,N,V
Rd ← Rd • Rd
Z,N,V
Rd ← Rd ⊕ Rd
Z,N,V
Rd ← $FF
None
R1:R0 ← Rd x Rr
Z,C
R1:R0 ← Rd x Rr
Z,C
R1:R0 ← Rd x Rr
Z,C
<< 1
R1:R0 ← (Rd x Rr)
Z,C
<< 1
R1:R0 ← (Rd x Rr)
Z,C
<< 1
R1:R0 ← (Rd x Rr)
Z,C
PC ← PC + k + 1
None
PC ← Z
None
PC ← k
None
PC ← PC + k + 1
None
PC ← Z
None
PC ← k
None
PC ← STACK
None
PC ← STACK
I
if (Rd = Rr) PC ← PC + 2 or 3
None
Rd − Rr
Z, N,V,C,H
Rd − Rr − C
Z, N,V,C,H
Rd − K
Z, N,V,C,H
if (Rr(b)=0) PC ← PC + 2 or 3
None
if (Rr(b)=1) PC ← PC + 2 or 3
None
if (P(b)=0) PC ← PC + 2 or 3
None
if (P(b)=1) PC ← PC + 2 or 3
None
if (SREG(s) = 1) then PC←PC+k + 1
None
if (SREG(s) = 0) then PC←PC+k + 1
None
if (Z = 1) then PC ← PC + k + 1
None
if (Z = 0) then PC ← PC + k + 1
None
if (C = 1) then PC ← PC + k + 1
None
if (C = 0) then PC ← PC + k + 1
None
if (C = 0) then PC ← PC + k + 1
None
if (C = 1) then PC ← PC + k + 1
None
if (N = 1) then PC ← PC + k + 1
None
if (N = 0) then PC ← PC + k + 1
None
if (N ⊕ V= 0) then PC ← PC + k + 1
None
if (N ⊕ V= 1) then PC ← PC + k + 1
None
if (H = 1) then PC ← PC + k + 1
None
if (H = 0) then PC ← PC + k + 1
None
if (T = 1) then PC ← PC + k + 1
None
#Clocks
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8154B–AVR–07/09