MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part NumberATMEGA16A-PU
DescriptionMCU AVR 16K FLASH 16MHZ 40-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA16A-PU datasheets
 


Specifications of ATMEGA16A-PU

Core ProcessorAVRCore Size8-Bit
Speed16MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o32
Program Memory Size16KB (8K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case40-DIP (0.600", 15.24mm)Processor SeriesATMEGA16x
CoreAVR8Data Bus Width8 bit
Data Ram Size1 KBInterface Type2-Wire/SPI/USART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os32
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitPackage40PDIP
Device CoreAVRFamily NameATmega
Maximum Speed16 MHzOperating Supply Voltage3.3|5 V
Controller Family/seriesAVR MEGANo. Of I/o's32
Eeprom Memory Size512ByteRam Memory Size1KB
Cpu Speed16MHzRohs CompliantYes
For Use WithATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KITLead Free Status / RoHS StatusLead free / RoHS Compliant
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Table 12-5.
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
12.3.2
Alternate Functions of Port B
The Port B pins with alternate functions are shown in
Table 12-6.
Port Pin
The alternate pin configuration is as follows:
• SCK – Port B, Bit 7
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a
Slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is
enabled as a Master, the data direction of this pin is controlled by DDB7. When the pin is forced
by the SPI to be an input, the pull-up can still be controlled by the PORTB7 bit.
• MISO – Port B, Bit 6
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a
Master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is
enabled as a Slave, the data direction of this pin is controlled by DDB6. When the pin is forced
by the SPI to be an input, the pull-up can still be controlled by the PORTB6 bit.
8154B–AVR–07/09
Overriding Signals for Alternate Functions in PA3:PA0
PA3/ADC3
PA2/ADC2
0
0
0
0
0
0
0
0
ADC3 INPUT
Port B Pins Alternate Functions
Alternate Functions
PB7
SCK (SPI Bus Serial Clock)
PB6
MISO (SPI Bus Master Input/Slave Output)
PB5
MOSI (SPI Bus Master Output/Slave Input)
PB4
SS (SPI Slave Select Input)
AIN1 (Analog Comparator Negative Input)
PB3
OC0 (Timer/Counter0 Output Compare Match Output)
AIN0 (Analog Comparator Positive Input)
PB2
INT2 (External Interrupt 2 Input)
PB1
T1 (Timer/Counter1 External Counter Input)
T0 (Timer/Counter0 External Counter Input)
PB0
XCK (USART External Clock Input/Output)
ATmega16A
PA1/ADC1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADC2 INPUT
ADC1 INPUT
Table
12-6.
PA0/ADC0
0
0
0
0
0
0
0
0
ADC0 INPUT
57