ATMEGA16A-PU | |
|---|---|
| Manufacturer Part Number | ATMEGA16A-PU |
| Description | MCU AVR 16K FLASH 16MHZ 40-PDIP |
| Manufacturer | Atmel |
| Series | AVR® ATmega |
| ATMEGA16A-PU datasheets |
|
Specifications of ATMEGA16A-PU | |||
|---|---|---|---|
| Core Processor | AVR | Core Size | 8-Bit |
| Speed | 16MHz | Connectivity | I²C, SPI, UART/USART |
| Peripherals | Brown-out Detect/Reset, POR, PWM, WDT | Number Of I /o | 32 |
| Program Memory Size | 16KB (8K x 16) | Program Memory Type | FLASH |
| Eeprom Size | 512 x 8 | Ram Size | 1K x 8 |
| Voltage - Supply (vcc/vdd) | 2.7 V ~ 5.5 V | Data Converters | A/D 8x10b |
| Oscillator Type | Internal | Operating Temperature | -40°C ~ 85°C |
| Package / Case | 40-DIP (0.600", 15.24mm) | Processor Series | ATMEGA16x |
| Core | AVR8 | Data Bus Width | 8 bit |
| Data Ram Size | 1 KB | Interface Type | 2-Wire/SPI/USART |
| Maximum Clock Frequency | 16 MHz | Number Of Programmable I/os | 32 |
| Number Of Timers | 3 | Maximum Operating Temperature | + 85 C |
| Mounting Style | Through Hole | 3rd Party Development Tools | EWAVR, EWAVR-BL |
| Development Tools By Supplier | ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT | Minimum Operating Temperature | - 40 C |
| On-chip Adc | 8-ch x 10-bit | Package | 40PDIP |
| Device Core | AVR | Family Name | ATmega |
| Maximum Speed | 16 MHz | Operating Supply Voltage | 3.3|5 V |
| Controller Family/series | AVR MEGA | No. Of I/o's | 32 |
| Eeprom Memory Size | 512Byte | Ram Memory Size | 1KB |
| Cpu Speed | 16MHz | Rohs Compliant | Yes |
| For Use With | ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
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Figure 19-2. Clock Generation Logic, Block Diagram
DDR_XCK
Signal description:
txclk
rxclk
xcki
operation.
xcko
fosc
19.3.1
Internal Clock Generation – The Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous Master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(fosc), is loaded with the UBRR value each time the counter has counted down to zero or when
the UBRRL Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= fosc/(UBRR+1)). The Transmitter divides the
baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-
put is used directly by the receiver’s clock and data recovery units. However, the recovery units
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSEL, U2X and DDR_XCK bits.
Table 19-1
ing the UBRR value for each mode of operation using an internally generated clock source.
8154B–AVR–07/09
UBRR
fosc
UBRR+1
Prescaling
Down-Counter
OSC
Sync
Edge
Register
Detector
xcki
XCK
xcko
Pin
UCPOL
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (Internal Signal). Used for synchronous Slave
Clock output to XCK pin (Internal Signal). Used for synchronous Master
operation.
XTAL pin frequency (System Clock).
contains equations for calculating the baud rate (in bits per second) and for calculat-
ATmega16A
U2X
/ 2
/ 4
/ 2
0
1
DDR_XCK
0
1
Figure
19-2.
0
txclk
1
UMSEL
1
rxclk
0
149
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