MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part NumberATMEGA16A-PU
DescriptionMCU AVR 16K FLASH 16MHZ 40-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA16A-PU datasheets
 


Specifications of ATMEGA16A-PU

Core ProcessorAVRCore Size8-Bit
Speed16MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o32
Program Memory Size16KB (8K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case40-DIP (0.600", 15.24mm)Processor SeriesATMEGA16x
CoreAVR8Data Bus Width8 bit
Data Ram Size1 KBInterface Type2-Wire/SPI/USART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os32
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitPackage40PDIP
Device CoreAVRFamily NameATmega
Maximum Speed16 MHzOperating Supply Voltage3.3|5 V
Controller Family/seriesAVR MEGANo. Of I/o's32
Eeprom Memory Size512ByteRam Memory Size1KB
Cpu Speed16MHzRohs CompliantYes
For Use WithATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KITLead Free Status / RoHS StatusLead free / RoHS Compliant
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Table 19-1.
Operating Mode
Asynchronous Normal Mode
(U2X = 0)
Asynchronous Double Speed Mode (U2X
= 1)
Synchronous Master Mode
Note:
BAUD
f
OSC
UBRR
Some examples of UBRR values for some system clock frequencies are found in
(see
page
19.3.2
Double Speed Operation (U2X)
The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect
for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
19.3.3
External Clock
External clocking is used by the synchronous Slave modes of operation. The description in this
section refers to
External clock input from the XCK pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and receiver. This process introduces
a two CPU clock period delay and therefore the maximum external XCK clock frequency is lim-
ited by the following equation:
Note that f
add some margin to avoid possible loss of data due to frequency variations.
19.3.4
Synchronous Clock Operation
When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxD) is sampled at the
opposite XCK clock edge of the edge the data output (TxD) is changed.
ATmega16A
150
Equations for Calculating Baud Rate Register Setting
BAUD
1. The baud rate is defined to be the transfer rate in bit per second (bps).
Baud rate (in bits per second, bps)
System Oscillator clock frequency
Contents of the UBRRH and UBRRL Registers, (0 - 4095)
171).
Figure 19-2
for details.
f
depends on the stability of the system clock source. It is therefore recommended to
osc
Equation for Calculating
Equation for Calculating
(1)
Baud Rate
UBRR Value
f
OSC
=
-------------------------------------- -
UBRR
(
)
16 UBRR
+
1
f
OSC
BAUD
=
---------------------------------- -
UBRR
(
)
8 UBRR
+
1
f
OSC
BAUD
=
---------------------------------- -
UBRR
(
)
2 UBRR
+
1
f
OSC
<
---------- -
XCK
4
f
OSC
=
----------------------- - 1
16BAUD
f
OSC
=
------------------- - 1
8BAUD
f
OSC
=
------------------- - 1
2BAUD
Table 19-9
8154B–AVR–07/09