MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part NumberATMEGA16A-PU
DescriptionMCU AVR 16K FLASH 16MHZ 40-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA16A-PU datasheets
 


Specifications of ATMEGA16A-PU

Core ProcessorAVRCore Size8-Bit
Speed16MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o32
Program Memory Size16KB (8K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case40-DIP (0.600", 15.24mm)Processor SeriesATMEGA16x
CoreAVR8Data Bus Width8 bit
Data Ram Size1 KBInterface Type2-Wire/SPI/USART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os32
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitPackage40PDIP
Device CoreAVRFamily NameATmega
Maximum Speed16 MHzOperating Supply Voltage3.3|5 V
Controller Family/seriesAVR MEGANo. Of I/o's32
Eeprom Memory Size512ByteRam Memory Size1KB
Cpu Speed16MHzRohs CompliantYes
For Use WithATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KITLead Free Status / RoHS StatusLead free / RoHS Compliant
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Page 126/352

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The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the out-
put will be continuously low and if set equal to MAX the output will be continuously high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of Period 2 in
there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-
TOM. There are two cases that will give transition without Compare Match:
• OCR2A changes its value from Max, like in
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCn value at MAX must be correspond the the result of an
up-counting Compare Match.
• The Timer starts counting from a value higher than the one in OCR2A, and for that reason
misses the Compare Match and hence the OCn that would have happened on the way up.
17.8
Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clk
is therefore shown as a clock enable signal. In Asynchronous mode, clk
the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are
set.
Figure 17-8
count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 17-8. Timer/Counter Timing Diagram, no Prescaling
clk
clk
(clk
TCNTn
TOVn
Figure 17-9
ATmega16A
126
Figure 17-7
contains timing data for basic Timer/Counter operation. The figure shows the
I/O
Tn
/1)
I/O
MAX - 1
shows the same timing data, but with the prescaler enabled.
OCn has a transition from high to l ow even though
Figure
17-7. When the OCR2A value is MAX the
should be replaced by
I/O
MAX
BOTTOM
)
T2
BOTTOM + 1
8154B–AVR–07/09