MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part NumberATMEGA16A-PU
DescriptionMCU AVR 16K FLASH 16MHZ 40-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA16A-PU datasheets
 


Specifications of ATMEGA16A-PU

Core ProcessorAVRCore Size8-Bit
Speed16MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o32
Program Memory Size16KB (8K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case40-DIP (0.600", 15.24mm)Processor SeriesATMEGA16x
CoreAVR8Data Bus Width8 bit
Data Ram Size1 KBInterface Type2-Wire/SPI/USART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os32
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitPackage40PDIP
Device CoreAVRFamily NameATmega
Maximum Speed16 MHzOperating Supply Voltage3.3|5 V
Controller Family/seriesAVR MEGANo. Of I/o's32
Eeprom Memory Size512ByteRam Memory Size1KB
Cpu Speed16MHzRohs CompliantYes
For Use WithATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KITLead Free Status / RoHS StatusLead free / RoHS Compliant
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A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
• Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types
of Pulse Width Modulation (PWM) modes.
Table 16-5.
Waveform Generation Mode Bit Description
WGM12
WGM11
Mode
WGM13
(CTC1)
(PWM11)
0
0
0
0
1
0
0
0
2
0
0
1
3
0
0
1
4
0
1
0
5
0
1
0
6
0
1
1
7
0
1
1
8
1
0
0
9
1
0
0
10
1
0
1
11
1
0
1
12
1
1
0
13
1
1
0
14
1
1
1
15
1
1
1
Note:
1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the
location of these bits are compatible with previous versions of the timer.
16.11.2
TCCR1B – Timer/Counter1 Control Register B
Bit
Read/Write
Initial Value
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is
activated, the input from the Input Capture Pin (ICP1) is filtered. The filter function requires four
successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the Noise Canceler is enabled.
ATmega16A
112
Table
16-5. Modes of operation supported by the Timer/Counter
(See “Modes of Operation” on page
(1)
WGM10
(PWM10)
Timer/Counter Mode of Operation
0
Normal
1
PWM, Phase Correct, 8-bit
0
PWM, Phase Correct, 9-bit
1
PWM, Phase Correct, 10-bit
0
CTC
1
Fast PWM, 8-bit
0
Fast PWM, 9-bit
1
Fast PWM, 10-bit
0
PWM, Phase and Frequency Correct
1
PWM, Phase and Frequency Correct
0
PWM, Phase Correct
1
PWM, Phase Correct
0
CTC
1
Reserved
0
Fast PWM
1
Fast PWM
WGM
7
6
5
4
ICNC1
ICES1
WGM13
R/W
R/W
R
R/W
0
0
0
0
99.)
Update of
TOV1 Flag Set
x
TOP
OCR1
on
0xFFFF
Immediate
MAX
0x00FF
TOP
BOTTOM
0x01FF
TOP
BOTTOM
0x03FF
TOP
BOTTOM
OCR1A
Immediate
MAX
0x00FF
BOTTOM
TOP
0x01FF
BOTTOM
TOP
0x03FF
BOTTOM
TOP
ICR1
BOTTOM
BOTTOM
OCR1A
BOTTOM
BOTTOM
ICR1
TOP
BOTTOM
OCR1A
TOP
BOTTOM
ICR1
Immediate
MAX
ICR1
BOTTOM
TOP
OCR1A
BOTTOM
TOP
12:0 definitions. However, the functionality and
3
2
1
0
WGM12
CS12
CS11
CS10
R/W
R/W
R/W
R/W
0
0
0
0
8154B–AVR–07/09
TCCR1B