MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part NumberATMEGA16A-PU
DescriptionMCU AVR 16K FLASH 16MHZ 40-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA16A-PU datasheets
 


Specifications of ATMEGA16A-PU

Core ProcessorAVRCore Size8-Bit
Speed16MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o32
Program Memory Size16KB (8K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case40-DIP (0.600", 15.24mm)Processor SeriesATMEGA16x
CoreAVR8Data Bus Width8 bit
Data Ram Size1 KBInterface Type2-Wire/SPI/USART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os32
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitPackage40PDIP
Device CoreAVRFamily NameATmega
Maximum Speed16 MHzOperating Supply Voltage3.3|5 V
Controller Family/seriesAVR MEGANo. Of I/o's32
Eeprom Memory Size512ByteRam Memory Size1KB
Cpu Speed16MHzRohs CompliantYes
For Use WithATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KITLead Free Status / RoHS StatusLead free / RoHS Compliant
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Figure 24-4. General Port Pin Schematic Diagram
Note:
24.5.2
Boundary-scan and the Two-wire Interface
The 2 Two-wire Interface pins SCL and SDA have one additional control signal in the scan-
chain; Two-wire Interface Enable – TWIEN. As shown in
a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. A general
scan cell as shown in
Notes:
8154B–AVR–07/09
PUExn
Pxn
IDxn
PUD:
PULLUP DISABLE
PUExn:
PULLUP ENABLE for pin Pxn
OCxn:
OUTPUT CONTROL for pin Pxn
ODxn:
OUTPUT DATA to pin Pxn
IDxn:
INPUT DATA from pin Pxn
SLEEP:
SLEEP CONTROL
1. See Boundary-scan description for details.
Figure 24-9
is attached to the TWIEN signal.
1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan
support for digital port pins suffice for connectivity tests. The only reason for having TWIEN in
the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary-
scan.
2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to
drive contention.
ATmega16A
(1)
Q
D
DDxn
Q
CLR
RESET
OCxn
Q
D
ODxn
PORTxn
Q
CLR
RESET
SLEEP
SYNCHRONIZER
D
Q
D
Q
PINxn
L
Q
Q
WDx:
WRITE DDRx
RDx:
READ DDRx
WPx:
WRITE PORTx
RRx:
READ PORTx REGISTER
RPx:
READ PORTx PIN
CLK
:
I/O CLOCK
I/O
Figure
24-5, the TWIEN signal enables
PUD
WDx
RDx
WPx
RRx
RPx
CLK
I/O
237