MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 122

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Clock Generator Module (CGMC)
7.6.6 PLL Reference Divider Select Register
Technical Data
122
NOTE:
NOTE:
NOTE:
Address:
PMDS may be called PRDS on other HC08 derivatives.
The PLL reference divider select register (PMDS) contains the
programming information for the modulo reference divider.
RDS3–RDS0 — Reference Divider Select Bits
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
The default divide value of 1 is recommended for all applications.
PMDS7–PMDS4 — Unimplemented Bits
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
These read/write bits control the modulo reference divider that selects
the reference division factor, R. (See
the
PCTL is set. A value of $00 in the reference divider select register
configures the reference divider the same as a value of $01. (See
Special Programming
$01 for a default divide value of 1.
These bits have no function and always read as logic 0s.
Figure 7-9. PLL Reference Divider Select Register (PMDS)
For More Information On This Product,
PLL.) RDS7–RDS0 cannot be written when the PLLON bit in the
$003B
Bit 7
0
0
Clock Generator Module (CGMC)
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= Unimplemented
6
0
0
Exceptions.) Reset initializes the register to
5
0
0
4
0
0
PLL Circuits
RDS3
3
0
MC68HC908GR8 — Rev 4.0
RDS2
2
0
and
RDS1
Programming
1
0
MOTOROLA
RDS0
Bit 0
1