MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 196

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Monitor ROM (MON)
15.4.2 Data Format
15.4.3 Break Signal
Technical Data
196
Table 15-2
mode.
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. Transmit and receive baud rates must
be identical.
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When
the monitor receives a break signal, it drives the PTA0 pin high for the
duration of two bits and then echoes back the break signal.
Freescale Semiconductor, Inc.
START
Monitor
Modes
BIT
For More Information On This Product,
User
0
BIT 0
1
summarizes the differences between user mode and monitor
Go to: www.freescale.com
2
MISSING STOP BIT
Monitor ROM (MON)
BIT 1
3
Vector
$FFFE
$FEFE
Reset
High
Figure 15-3. Monitor Data Format
Figure 15-4. Break Transaction
4
Table 15-2. Mode Differences
BIT 2
5
6
Vector
$FEFF
$FFFF
BIT 3
Reset
Low
7
BIT 4
$FEFC
Vector
$FFFC
Break
High
BIT 5
Functions
2-STOP BIT DELAY BEFORE ZERO ECHO
BIT 6
0
$FEFD
Vector
$FFFD
Break
Low
MC68HC908GR8 — Rev 4.0
1
BIT 7
2
3
STOP
$FEFC
Vector
$FFFC
BIT
High
SWI
4
START
NEXT
5
BIT
MOTOROLA
6
Vector
$FFFD
$FEFD
Low
SWI
7