MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 187

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

14.4.4 LVI Trip Selection
14.5 LVI Status Register
MC68HC908GR8 — Rev 4.0
MOTOROLA
NOTE:
Address:
The LVI5OR3 bit in the configuration register selects whether the LVI is
configured for 5V or 3V protection.
The microcontroller is guaranteed to operate at a minimum supply
voltage. The trip point (V
this. (See
The LVI status register (LVISR) indicates if the V
detected below the V
LVIOUT — LVI Output Bit
Reset:
Read: LVIOUT
Write:
This read-only flag becomes set when the V
V
Freescale Semiconductor, Inc.
TRIPF
For More Information On This Product,
$FE0C
Bit 7
0
trip voltage. See
Electrical Specifications
Go to: www.freescale.com
V
Figure 14-3. LVI Status Register (LVISR)
Low-Voltage Inhibit (LVI)
TRIPF
= Unimplemented
V
V
6
0
0
DD
Table 14-1. LVIOUT Bit Indication
DD
V
V
> V
TRIPF
DD
DD
V
TRIPR
TRIPF
TRIPF
5
0
0
V
level.
Table
TRIPR
[5 V] or V
14-1. Reset clears the LVIOUT bit.
4
0
0
for the actual trip point voltages.)
TRIPF
3
0
0
Previous value
LVIOUT
[3 V]) may be lower than
DD
0
1
DD
voltage falls below the
2
0
0
Low-Voltage Inhibit (LVI)
voltage was
LVI Status Register
1
0
0
Technical Data
Bit 0
0
0
187