MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 321

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.13.5 CGND (Clock Ground)
MC68HC908GR8 — Rev 4.0
MOTOROLA
When an SPI is configured as a master, the SS input can be used in
conjunction with the MODF flag to prevent multiple masters from driving
MOSI and SPSCK. See
set the MODF flag, the MODFEN bit in the SPSCK register must be set.
If the MODFEN bit is low for an SPI master, the SS pin can be used as
a general-purpose I/O under the control of the data direction register of
the shared I/O port. With MODFEN high, it is an input-only pin to the SPI
regardless of the state of the data direction register of the shared I/O
port.
The CPU can always read the state of the SS pin by configuring the
appropriate pin as an input and reading the port data register. See
20-3.
CGND is the ground return for the serial clock pin, SPSCK, and the
ground for the port output buffers. It is internally connected to V
shown in
Note 1. X = Don’t care
SPE
Freescale Semiconductor, Inc.
0
1
1
1
For More Information On This Product,
SPMSTR
Table
X
Serial Peripheral Interface (SPI)
0
1
1
(1)
Go to: www.freescale.com
20-1.
MODFEN
Table 20-3. SPI Configuration
X
X
0
1
Mode Fault
Master without MODF
SPI Configuration
Master with MODF
Not enabled
Error. For the state of the SS pin to
Slave
Serial Peripheral Interface (SPI)
General-purpose I/O;
General-purpose I/O;
State of SS Logic
SS ignored by SPI
SS ignored by SPI
Input-only to SPI
Input-only to SPI
Technical Data
I/O Signals
SS
Table
as
321