MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 260

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Serial Communications Interface (SCI)
18.9.4 SCI Status Register 1
Technical Data
260
Address:
PEIE — Receiver Parity Error Interrupt Enable Bit
SCI status register 1 (SCS1) contains flags to signal these conditions:
SCTE — SCI Transmitter Empty Bit
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
This read/write bit enables SCI receiver CPU interrupt requests
generated by the parity error bit, PE. See
Reset clears PEIE.
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This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal
For More Information On This Product,
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to SCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing error
Parity error
Serial Communications Interface (SCI)
$0016
SCTE
Bit 7
1
Figure 18-12. SCI Status Register 1 (SCS1)
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= Unimplemented
TC
6
1
SCRF
5
0
IDLE
0
4
OR
3
0
SCI Status Register
MC68HC908GR8 — Rev 4.0
NF
2
0
FE
1
0
MOTOROLA
1.
Bit 0
PE
0