MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 271

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Technical Data — MC68HC908GR8
19.1 Contents
19.2 Introduction
MC68HC908GR8 — Rev 4.0
MOTOROLA
Section 19. System Integration Module (SIM)
19.2
19.3
19.4
19.5
19.6
19.7
19.8
This section describes the system integration module (SIM). Together
with the CPU, the SIM controls all MCU activities. A block diagram of the
SIM is shown in
input/output (I/O) registers. The SIM is a system state controller that
coordinates CPU and exception timing. The SIM is responsible for:
Freescale Semiconductor, Inc.
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Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
Master reset control, including power-on reset (POR) and COP
timeout
Interrupt control:
– Acknowledge timing
– Arbitration control timing
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 275
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 276
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
System Integration Module (SIM)
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Figure
19-1.
Table 19-1
is a summary of the SIM
Technical Data
271