MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 296

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
19.8.3 SIM Break Flag Control Register
Technical Data
296
Address:
ILAD — Illegal Address Reset Bit (opcode fetches only)
MODRST — Monitor Mode Entry Module Reset Bit
LVI — Low-Voltage Inhibit Reset Bit
The SIM break control register contains a bit that enables software to
clear status bits while the MCU is in a break state.
BCFE — Break Clear Flag Enable Bit
Reset:
Read:
Write:
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 19-22. SIM Break Flag Control Register (SBFCR)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
1 = Last reset caused by monitor mode entry when vector locations
0 = POR or read of SRSR
1 = Last reset caused by the LVI circuit
0 = POR or read of SRSR
1 = Status bits clearable during break
0 = Status bits not clearable during break
$FE03
BCFE
Bit 7
$FFFE and $FFFF are $00 after POR while IRQ = V
R
0
System Integration Module (SIM)
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= Reserved
R
6
R
5
R
4
R
3
MC68HC908GR8 — Rev 4.0
R
2
R
1
MOTOROLA
DD
Bit 0
R