MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 64

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Resets and Interrupts
4.3.3.3 Low-Voltage Inhibit Reset
4.3.3.4 Illegal Opcode Reset
4.3.3.5 Illegal Address Reset
Technical Data
64
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in
the power supply voltage to the LVI trip voltage, V
An LVI reset:
An illegal opcode reset is an internal reset caused by an opcode that is
not in the instruction set. An illegal opcode reset sets the ILOP bit in the
SIM reset status register.
If the stop enable bit, STOP, in the mask option register is a logic 0, the
STOP instruction causes an illegal opcode reset.
An illegal address reset is an internal reset caused by opcode fetch from
an unmapped address. An illegal address reset sets the ILAD bit in the
SIM reset status register.
A data fetch from an unmapped address does not generate a reset.
Freescale Semiconductor, Inc.
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For More Information On This Product,
Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles after the power
supply voltage rises to V
Drives the RST pin low for as long as V
during the oscillator stabilization delay
Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay
Releases the CPU to begin the reset vector sequence
64 CGMXCLK cycles after the oscillator stabilization delay
Sets the LVI bit in the SIM reset status register
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Resets and Interrupts
TRIPF
DD
MC68HC908GR8 — Rev 4.0
is below V
TRIPF
.
TRIPF
MOTOROLA
and