MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 85

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.8 I/O Registers
5.8.1 ADC Status and Control Register
MC68HC908GR8 — Rev 4.0
MOTOROLA
CAUTION:
Address: $0003C
These I/O registers control and monitor ADC operation:
Function of the ADC status and control register (ADSCR) is described
here.
COCO/IDMAS — Conversions Complete/Interrupt DMA Select Bit
Because the MC68HC908GR8 does NOT have a DMA module, the
IDMAS bit should NEVER be set when AIEN is set. Doing so will mask
ADC interrupts and cause unwanted results.
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
•
•
•
When the AIEN bit is a logic 0, the COCO/IDMAS is a read-only bit
which is set each time a conversion is completed except in the
continuous conversion mode where it is set after the first conversion.
This bit is cleared whenever the ADSCR is written or whenever the
ADR is read.
If the AIEN bit is a logic 1, the COCO/IDMAS is a read/write bit which
selects either CPU or DMA to service the ADC interrupt request.
Reset clears this bit.
For More Information On This Product,
1 = Conversion completed (AIEN = 0)/DMA interrupt (AIEN = 1)
0 = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN = 1)
Figure 5-2. ADC Status and Control Register (ADSCR)
ADC status and control register (ADSCR)
ADC data register (ADR)
ADC clock register (ADCLK)
COCO/
IDMAS
Bit 7
Analog-to-Digital Converter (ADC)
0
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AIEN
6
0
ADCO
5
0
ADCH4
4
1
ADCH3
3
1
Analog-to-Digital Converter (ADC)
ADCH2
2
1
ADCH1
1
1
Technical Data
I/O Registers
ADCH0
Bit 0
1
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