MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 299

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.5 Functional Description
MC68HC908GR8 — Rev 4.0
MOTOROLA
Addr.
$0010
$0011
$0012
SPI Status and Control
Register Name
Pin Names:
SPI Control Register
Full SPI
Register (SPSCR)
SPI Data Register
SPI Generic
Pin Names:
(SPCR)
(SPDR)
SPI
The full names of the SPI I/O pins are shown in
pin names appear in the text that follows.
Figure 20-1
structure of the SPI module.
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Freescale Semiconductor, Inc.
Figure 20-1. SPI I/O Register Summary
For More Information On This Product,
Table 20-1. Pin Name Conventions
PTD1/ATD9
SPRIE
SPRF
Bit 7
MISO
R7
T7
0
0
Serial Peripheral Interface (SPI)
summarizes the SPI I/O registers and
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= Unimplemented
ERRIE
DMAS
R6
T6
6
0
0
PTD2/ATD1
MOSI
SPMSTR
0
OVRF
R5
T5
5
1
0
Unaffected by reset
PTD0/AT
MODF
CPOL
R4
T4
4
0
0
SS
D8
CPHA
SPTE
R3
T3
3
1
1
PTD3/ATD11
Serial Peripheral Interface (SPI)
SPSCK
Table
SPWOM
MODFEN
Figure 20-2
R2
T2
2
0
0
Functional Description
20-1. The generic
SPR1
SPE
CGND
R1
T1
1
0
0
Technical Data
V
SS
shows the
SPTIE
Bit 0
SPR0
R0
T0
0
0
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