MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 277

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.4.1 External Pin Reset
19.4.2 Active Resets from Internal Sources
MC68HC908GR8 — Rev 4.0
MOTOROLA
CGMOUT
RST
IAB
NOTE:
PC
An internal reset clears the SIM counter (see
external reset does not. Each of the resets sets a corresponding bit in
the SIM reset status register (SRSR). See
The RST pin circuit includes an internal pullup device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the SIM
reset status register (SRSR) is set as long as RST is held low for a
minimum of 67 CGMXCLK cycles, assuming that neither the POR nor
the LVI was the source of the reset. See
19-4
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles. See
19-5. An internal reset can be caused by an illegal address, illegal
opcode, COP timeout, LVI, or POR. See
For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal
Freescale Semiconductor, Inc.
For More Information On This Product,
shows the relative timing.
Figure 19-4. External Reset Timing
Reset Type
All others
POR/LVI
System Integration Module (SIM)
Go to: www.freescale.com
Table 19-2. PIN Bit Set Timing
Number of Cycles Required to Set PIN
VECT H VECT L
4163 (4096 + 64 + 3)
Table 19-2
Figure
67 (64 + 3)
SIM
System Integration Module (SIM)
SIM
Reset and System Initialization
Registers.
19-6.
Counter), but an
for details.
Technical Data
Figure
Figure
277