MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 22

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

List of Figures
Technical Data
22
19-3 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
19-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
19-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
19-6 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
19-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
19-8 Interrupt Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
19-9 Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
19-10 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
19-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . 285
19-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . .288
19-13 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . .288
19-14 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . .289
19-15 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
19-16 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . 291
19-17 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . 292
19-18 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
19-19 Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . . 293
19-20 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . 294
19-21 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . 295
19-22 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . 296
20-1 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
20-2 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 300
20-3 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . . 301
20-4 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . 305
20-5 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
20-6 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . 306
20-7 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . . 308
20-8 .SPRF/SPTE CPU Interrupt Timing . . . . . . . . . . . . . . . . . . . . 309
20-9 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . . 311
20-10 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . . 312
20-11 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . . 315
20-12 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
20-13 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . 322
20-14 SPI Status and Control Register (SPSCR) . . . . . . . . . . . . . . .325
20-15 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
21-1 Timebase Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
21-2 Timebase Control Register (TBCR) . . . . . . . . . . . . . . . . . . . . 331
22-1 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
List of Figures
MC68HC908GR8 — Rev 4.0
MOTOROLA