MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 184

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Low-Voltage Inhibit (LVI)
14.4 Functional Description
Technical Data
184
NOTE:
NOTE:
Figure 14-1
out of reset. The LVI module contains a bandgap reference circuit and
comparator. Clearing the LVI power disable bit, LVIPWRD, enables the
LVI to monitor V
enables the LVI module to generate a reset when V
point voltage, V
enables the LVI to operate in stop mode. Setting the LVI 5V or 3V trip
point bit, LVI5OR3, enables V
Clearing the LVI5OR3 bit enables V
operation. The actual trip points are shown in
After a power-on reset (POR) the LVI’s default mode of operation is 3 V.
If a 5V system is used, the user must set the LVI5OR3 bit to raise the trip
point to 5V operation. Note that this must be done after every POR since
the default will revert back to 3V mode after each POR. If the V
is below the 5V mode trip voltage but above the 3V mode trip voltage
when POR is released, the part will operate because V
3V mode after a POR. So, in a 5V system care must be taken to ensure
that V
If the user requires 5V mode and sets the LVI5OR3 bit after a POR while
the V
immediately go into reset. The LVI in this case will hold the part in reset
until either V
release reset or V
the POR and reset the trip point to 3V operation.
Freescale Semiconductor, Inc.
For More Information On This Product,
DD
DD
supply is not above the V
is above the 5V mode trip voltage after POR is released.
shows the structure of the LVI module. The LVI is enabled
Go to: www.freescale.com
DD
Low-Voltage Inhibit (LVI)
TRIPF
goes above the rising 5V trip point, V
DD
DD
voltage. Clearing the LVI reset disable bit, LVIRSTD,
decreases to approximately 0 V which will re-trigger
. Setting the LVI enable in stop mode bit, LVISTOP,
TRIPF
TRIPR
to be configured for 5V operation.
TRIPF
for 5V mode, the MCU will
to be configured for 3V
Electrical
MC68HC908GR8 — Rev 4.0
DD
TRIPR
falls below the trip
TRIPF
Specifications.
, which will
defaults to
MOTOROLA
DD
supply