MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet - Page 325

• Manufacturer Part Number: MCHC908GR8CFAE
• Description: IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08G
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908GR8 — Rev 4.0
MOTOROLA
Address: $0011
SPRF — SPI Receiver Full Bit
ERRIE — Error Interrupt Enable Bit
OVRF — Overflow Bit
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
This clearable, read-only flag is set each time a byte transfers from
the shift register to the receive data register. SPRF generates a CPU
interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the
SPI status and control register with SPRF set and then reading the
SPI data register.
Reset clears the SPRF bit.
This read/write bit enables the MODF and OVRF bits to generate
CPU interrupt requests. Reset clears the ERRIE bit.
This clearable, read-only flag is set if software does not read the byte
in the receive data register before the next full byte enters the shift
register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the
OVRF bit by reading the SPI status and control register with OVRF set
and then reading the receive data register. Reset clears the OVRF bit.
For More Information On This Product,
Figure 20-14. SPI Status and Control Register (SPSCR)
1 = Receive data register full
0 = Receive data register not full
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
1 = Overflow
0 = No overflow
SPRF
Bit 7
0
Serial Peripheral Interface (SPI)
Go to: www.freescale.com
= Unimplemented
ERRIE
6
0
OVRF
5
0
MODF
4
0
SPTE
3
1
Serial Peripheral Interface (SPI)
MODFEN
2
0
SPR1
1
0
Technical Data
I/O Registers
SPR0
Bit 0
0
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