AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 103

• Manufacturer Part Number: AT91SAM7X128-CU
• Description: MCU ARM 128K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19. Embedded Flash Controller (EFC)
19.1
19.2
19.2.1
6120H–ATARM–17-Feb-09
Overview
Functional Description
Embedded Flash Organization
The Embedded Flash Controller (EFC ) is a part of the Memory Controller and ensures the inter-
face of the Flash block with the 32-bit internal bus. It increases performance in Thumb Mode for
Code Fetch with its system of 32-bit buffers. It also manages the programming, erasing, locking
and unlocking sequences using a full set of commands.
The AT91SAM7X512 is equipped with two EFCs, EFC0 and EFC1. EFC1 does not feature the
Security bit and GPNVM bits. The Security and GPNVM bits embedded only on EFC0 apply to
the two blocks in the AT91SAM7X512.
The Embedded Flash interfaces directly to the 32-bit internal bus. It is composed of several
interfaces:
The Embedded Flash size, the page size and the lock region organization are described in the
product definition section.
Table 19-1.
AT91SAM7X512
• One memory plane organized in several pages of the same size
• Two 32-bit read buffers used for code read optimization (see
• One write buffer that manages page programming. The write buffer size is equal to the page
• Several lock bits used to protect write and erase operations on lock regions. A lock region is
• Several general-purpose NVM bits. Each bit controls a specific feature in the device. Refer to
104).
size. This buffer is write-only and accessible all along the 1 MByte address space, so that
each word can be written to its final address (see
composed of several consecutive pages, and each lock region has its associated lock bit.
the product definition section to get the GPNVM assignment.
32
3
Product Specific Lock and General-purpose NVM Bits
AT91SAM7X256
AT91SAM7X512/256/128 Preliminary
16
3
AT91SAM7X128 Denomination
3
8
“Write Operations” on page
Number of General-purpose NVM bits
Number of Lock Bits
“Read Operations” on page
106).
103