AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 456

• Manufacturer Part Number: AT91SAM7X128-CU
• Description: MCU ARM 128K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 34-6. Data IN Transfer for Non Ping-pong Endpoint
456
USB Bus Packets
TXPKTRDY Flag
(UDP_CSRx)
TXCOMP Flag
(UDP_CSRx)
FIFO (DPR)
Content
Using Endpoints With Ping-pong Attribute
AT91SAM7X512/256/128 Preliminary
Set by the firmware
Data IN
PID
Prevous Data IN TX
Data IN 1
Interrupt Pending
The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This
also allows handling the maximum bandwidth defined in the USB specification during bulk trans-
fer. To be able to guarantee a constant or the maximum bandwidth, the microcontroller must
prepare the next data payload to be sent while the current one is being sent by the USB device.
Thus two banks of memory are used. While one is available for the microcontroller, the other
one is locked by the USB device.
Figure 34-7. Bank Swapping Data IN Transfer for Ping-pong Endpoints
Cleared by Hw
Data IN 1
Microcontroller
1 st Data Payload
2 nd Data Payload
3 rd Data Payload
DPR access by the firmware
ACK
PID
Load In Progress
Set by the firmware
Microcontroller Load Data in FIFO
Data IN
PID
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Write
NAK
PID
Cleared by Firmware
USB Device
Data IN
PID
DPR access by the hardware
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Read
Read and Write at the Same Time
Data is Sent on USB Bus
Data IN 2
Payload in FIFO
Data IN 2
USB Bus
Cleared by Hw
2 nd Data Payload
3 rd Data Payload
1 st Data Payload
Data IN Packet
Data IN Packet
Data IN Packet
6120H–ATARM–17-Feb-09
ACK
PID
Cleared by
Firmware
Interrupt
Pending