AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 286

• Manufacturer Part Number: AT91SAM7X128-CU
• Description: MCU ARM 128K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

29.5.5
29.5.5.1
Figure 29-10. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 29-11. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
286
TWD
TWD
TWD
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
Three bytes internal address
Two bytes internal address
One byte internal address
S
S
S
AT91SAM7X512/256/128 Preliminary
S
S
S
Internal Address
7-bit Slave Addressing
DADR
DADR
DADR
DADR
DADR
DADR
W
W
W
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address
devices and 10-bit slave address devices.
When Addressing 7-bit slave devices, the internal address bytes are used to perform random
address (read or write) accesses to reach one or more data bytes, within a memory page loca-
tion in a serial memory, for example. When performing read operations with an internal address,
the TWI performs a write operation to set the internal address into the slave device, and then
switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is
sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See
29-11
The three internal address bytes are configurable through the Master Mode register
(TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to
0.
In the figures below the following abbreviations are used:
W
W
W
• S
• P
• W
• R
• A
• N
• DADR
• IADR
A
A
A
and
A
A
A
IADR(23:16)
IADR(15:8)
IADR(7:0)
Figure
IADR(23:16)
Start
Stop
Write
Read
Acknowledge
Not Acknowledge
Device Address
Internal Address
IADR(15:8)
IADR(7:0)
29-12.
A
A
A
IADR(15:8)
A
A
A
IADR(7:0)
S
DADR
IADR(15:8)
IADR(7:0)
DATA
A
A
R
IADR(7:0)
S
A
A
A
A
DADR
IADR(7:0)
P
DATA
DATA
A
S
R
A
A
A
N
DADR
DATA
P
DATA
P
DATA
Figure
6120H–ATARM–17-Feb-09
R
N
29-10,
A
P
A
N
P
P
Figure