AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 310

• Manufacturer Part Number: AT91SAM7X128-CU
• Description: MCU ARM 128K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 30-4. Fractional Baud Rate Generator
30.6.1.4
30.6.1.5
310
SCK
Reserved
MCK/DIV
AT91SAM7X512/256/128 Preliminary
MCK
Baud Rate in Synchronous Mode
Baud Rate in ISO 7816 Mode
USCLKS
0
1
2
3
If the USART is programmed to operate in synchronous mode, the selected clock is simply
divided by the field CD in US_BRGR.
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided
directly by the signal on the USART SCK pin. No division is active. The value written in
US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the
system clock.
When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the
value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the
SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty
cycle on the SCK pin, even if the value programmed in CD is odd.
The ISO7816 specification defines the bit rate with the following formula:
where:
• B is the bit rate
• Di is the bit-rate adjustment factor
• Fi is the clock frequency division factor
• f is the ISO7816 clock frequency (Hz)
BaudRate
16-bit Counter
CD
B
Modulus
=
Control
=
FP
SelectedClock
------------------------------------- -
Di
----- -
Fi
×
CD
f
glitch-free
USCLKS = 3
logic
FP
SYNC
0
CD
>1
1
0
1
0
OVER
Sampling
Divider
FIDI
0
1
6120H–ATARM–17-Feb-09
SYNC
SCK
Baud Rate
Sampling
Clock
Clock