AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 580

• Manufacturer Part Number: AT91SAM7X128-CU
• Description: MCU ARM 128K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

37.5.1
Register Name:
Access Type:
• LB: LoopBack
Asserts the loopback signal to the PHY.
• LLB: Loopback Local
Connects txd to rxd, tx_en to rx_dv, forces full duplex and drives rx_clk and tx_clk with pclk divided by 4.
rx_clk and tx_clk may glitch as the EMAC is switched into and out of internal loop back. It is important that receive
and transmit circuits have already been disabled when making the switch into and out of internal loop back.
• RE: Receive Enable
When set, enables the EMAC to receive data. When reset, frame reception stops immediately and the receive FIFO is
cleared. The receive queue pointer register is unaffected.
• TE: Transmit Enable
When set, enables the Ethernet transmitter to send data. When reset transmission, stops immediately, the transmit FIFO
and control registers are cleared and the transmit queue pointer register resets to point to the start of the transmit descrip-
tor list.
• MPE: Management Port Enable
Set to one to enable the management port. When zero, forces MDIO to high impedance state and MDC low.
• CLRSTAT: Clear Statistics Registers
This bit is write only. Writing a one clears the statistics registers.
• INCSTAT: Increment Statistics Registers
This bit is write only. Writing a one increments all the statistics registers by one for test purposes.
• WESTAT: Write Enable for Statistics Registers
Setting this bit to one makes the statistics registers writable for functional test purposes.
• BP: Back Pressure
If set in half duplex mode, forces collisions on all received frames.
• TSTART: Start Transmission
Writing one to this bit starts transmission.
580
WESTAT
31
23
15
–
–
–
7
AT91SAM7X512/256/128 Preliminary
Network Control Register
INCSTAT
30
22
14
EMAC_NCR
–
–
–
6
Read-write
CLRSTAT
29
21
13
–
–
–
5
MPE
28
20
12
–
–
–
4
TE
27
19
11
–
–
–
3
THALT
RE
26
18
10
–
–
2
TSTART
LLB
25
17
–
–
9
1
6120H–ATARM–17-Feb-09
BP
LB
24
16
–
–
8
0