AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 49

• Manufacturer Part Number: AT91SAM7X128-CU
• Description: MCU ARM 128K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.5.4.1
6120H–ATARM–17-Feb-09
JTAG Boundary-scan Register
with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1
JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be per-
formed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.
The Boundary-scan Register (BSR) contains 187 bits that correspond to active pins and associ-
ated control signals.
Each AT91SAM7X input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit
contains data that can be forced on the pad. The INPUT bit facilitates the observability of data
applied to the pad. The CONTROL bit selects the direction of the pad.
Table 12-2.
Number
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
Bit
AT91SAM7X JTAG Boundary Scan Register
AT91SAM7X512/256/128 Preliminary
PA2/SCK0/SPI1_NPCS1
PA3/RTS0/SPI1_NPCS2
PA4/CTS0/SPI1_NPCS3
PA30/IRQ0/PCK2
PA0/RXD0
PA5/RXD1
Pin Name
PA1/TXD0
PA6/TXD1
Pin Type
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
Associated BSR
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Cells
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