AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 663

• Manufacturer Part Number: AT91SAM7X128-CU
• Description: MCU ARM 128K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

41.4.5.4
41.4.6
41.4.6.1
41.4.7
41.4.7.1
41.4.7.2
41.4.7.3
41.4.7.4
6120H–ATARM–17-Feb-09
Real Time Timer (RTT)
Serial Peripheral Interface (SPI)
PWM: Behavior of CHIDx Status Bits in the PWM_SR Register
RTT: Possible Event Loss when Reading RTT_SR
SPI: Bad tx_ready Behavior when CSAAT = 1 and SCBR = 1
SPI: LASTXFER (Last Transfer) Behavior
SPI: Chip Select and Fixed Mode
SPI: SPCK Behavior in Master Mode
Erratic behavior of the CHIDx status bit in the PWM_SR Register. When a channel is disabled
by writing in the PWM_DIS Register just after enabling it (before completion of a Clock Period of
the clock selected for the channel), the PWM line is internally disabled but the CHIDx status bit
in the PWM_SR stays at 1.
Do not disable a channel before completion of one period of the selected clock.
If an event (RTTINC or ALMS) occurs within the same slow clock cycle during which the
RTT_SR is read, the corresponding bit might be cleared. This can lead to the loss of this event.
The software must handle the RTT event as an interrupt and should not poll RTT_SR.
If the SPI2 is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are per-
formed consecutively on the same slave with an IDLE state between them, the tx_ready signal
does not rise after the second data has been transferred in the shifter. This can imply for exam-
ple, that the second data is sent twice.
Do not use the combination CSAAT = 1 and SCBR = 1.
In FIXED Mode, with CSAAT bit set, and in “PDC mode” the Chip Select can rise depending on
the data written in the SPI_TDR when the TX_EMPTY flag is set. If for example, the PDC writes
a “1” in the bit 24 (LASTXFER bit) of the SPI_TDR, the chip select will rise as soon as the
TXEMPTY flag is set.
Use the CS in PIO mode when PDC mode is required and CS has to be maintained between
transfers.
SPCK pin can toggle out before the first transfer in Master Mode.
In Master Mode, MSTR bit must be set (in SPI_MR register) before configuring SPI_CSRx
registers.
In fixed Mode, if a transfer is performed through a PDC on a Chip select different from the Chip
select 0, the output spi_size sampled by the PDC will depend on the field, BITS (Bits per Trans-
fer) of SPI_CSR0 register, whatever the selected Chip select is. For example, if SPI_CSR0 is
configured for a 10-bit transfer whereas SPI_CSR1 is configured for an 8-bit transfer, when a
Problem Fix/Workaround
Problem Fix/Workaround:
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM7X512/256/128 Preliminary
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