AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 427

• Manufacturer Part Number: AT91SAM7X128-CU
• Description: MCU ARM 128K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6120H–ATARM–17-Feb-09
Figure 33-4. Non Overlapped Center Aligned Waveforms
Note:
• the waveform duty cycle. This channel parameter is defined in the CDTY field of the
• the waveform polarity. At the beginning of the period, the signal can be at high or low level.
• the waveform alignment. The output waveform can be left or center aligned. Center aligned
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
PWM_CDTYx register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
This property is defined in the CPOL field of the PWM_CMRx register. By default the signal
starts by a low level.
waveforms can be used to generate non overlapped waveforms. This property is defined in
the CALG field of the PWM_CMRx register. The default mode is left aligned.
(
------------------------------------------ -
(
------------------------------------------ -
(
----------------------------------------------------- -
PWM0
PWM1
CRPD
2
2
duty cycle
duty cycle
×
×
X
CPRD
See
MCK
MCK
×
MCK
×
CPRD
Figure 33-5 on page 429
DIVA
×
=
DIVA
=
No overlap
)
)
(
----------------------------------------------------------------------------------------------------------- -
(
----------------------------------------------------------------------------------------------------------------------------- -
period 1
or
(
period
)
(
---------------------------------------------- -
or
CRPD
AT91SAM7X512/256/128 Preliminary
Period
(
----------------------------------------------------- -
–
2
⁄
MCK
×
×
2
⁄
CPRD
) 1
DIVAB
fchannel_x_clock
–
MCK
for a detailed description of center aligned waveforms.
period
⁄
(
×
period
)
fchannel_x_clock
DIVB
)
⁄
2
)
×
CDTY
×
CDTY
)
) )
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