AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 649

• Manufacturer Part Number: AT91SAM7X128-CU
• Description: MCU ARM 128K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

41.2.9.4
41.2.9.5
41.2.10
41.2.10.1
41.2.10.2
41.2.10.3
41.2.10.4
6120H–ATARM–17-Feb-09
Universal Synchronous Asynchronous Receiver Transmitter (USART)
USART: CTS in Hardware Handshaking
USART: Hardware Handshaking – Two Characters Sent
USART: RXBRK Flag Error in Asynchronous Mode
USART: DCD is Active High instead of Low.
TWI: Possible Receive Holding Register Corruption
TWI: Software Reset
TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of
the TWI_SR.
When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the
TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor
OVERRUN status bits are set if this occurs.
The user must be sure that received data is read before transmitting any new data.
when a software reset is performed during a frame and when TWCK is low, it is impossible to ini-
tiate a new transfer in READ or WRITE mode.
None.
When Hardware Handshaking is used and if CTS goes low near the end of the start bit, a char-
acter can be lost.
CTS must not go high during a time slot occurring between 2 Master Clock periods before and
16 Master Clock periods after the rising edge of the start bit.
None.
If CTS switches from 0 to 1 during the TX of a character and if the holding register (US_THR) is
not empty, the content of US_THR will also be transmitted.
Don't use the PDC in transmit mode and do not fill US_THR before TXEMPTY is set at 1.
When timeguard is 0, RXBRK is not set when the break character is located just after the Stop
bit. FRAME (Frame Error) is set instead.
Timeguard should be > 0.
The DCD signal is active at High level in the USART Modem Mode .
DCD should be active at Low level.
Add an inverter.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM7X512/256/128 Preliminary
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