AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 462
AT91SAM7X128-CU
Manufacturer Part Number
AT91SAM7X128-CU
Description
MCU ARM 128K HS FLASH 100-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7X512-AU-999.pdf
(687 pages)
Specifications of AT91SAM7X128-CU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7X128-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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34.5.2.5
34.5.2.6
462
Endpoints Without Dual-Banks
Endpoints With Dual-Banks
AT91SAM7X512/256/128 Preliminary
Transmit Data Cancellation
Reset the endpoint to clear the FIFO (pointers). (See,
Some endpoints have dual-banks whereas some endpoints have only one bank. The procedure
to cancel transmission data held in these banks is described below.
To see the organization of dual-bank availablity refer to
There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In
the other instance, TXPKTRDY is not set.
There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In
the other instance, TXPKTRDY is not set.
• TXPKTRDY is not set:
• TXPKTRDY has already been set:
• TXPKTRDY is not set:
• TXPKTRDY has already been set:
– Reset the endpoint to clear the FIFO (pointers). (See,
– Clear TXPKTRDY so that no packet is ready to be sent
– Reset the endpoint to clear the FIFO (pointers). (See,
– Reset the endpoint to clear the FIFO (pointers). (See,
– Clear TXPKTRDY and read it back until actually read at 0.
– Set TXPKTRDY and read it back until actually read at 1.
– Clear TXPKTRDY so that no packet is ready to be sent.
Endpoint
Endpoint
Endpoint
Register”.)
Register”.)
Register”.)
Section 34.6.9 ”UDP Reset Endpoint
Table 34-1 ”USB Endpoint
Section 34.6.9 ”UDP Reset
Section 34.6.9 ”UDP Reset
Section 34.6.9 ”UDP Reset
6120H–ATARM–17-Feb-09
Register”.)
Description”.
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