AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 673

• Manufacturer Part Number: AT91SAM7X128-CU
• Description: MCU ARM 128K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6120H–ATARM–17-Feb-09
Version
6120G
(Continued) Comments
Electrical Characteristics,
Table 38-6, “Power Consumption for Different
assigned to Flash In standby mode. Footnote assigned to Ultra Low Power mode.
Section 38.7 ”ADC
“Transfer
Table 38-9, “Main Oscillator
Table 38-11, “XIN Clock Electrical
Figure 38-2, ”XIN CLock Timing” on page
Table 38-2, “DC
Section 39.1 “Thermal Conditions”, removed.
Table 39-3, “Package Reference”
Errata,
“AT91SAM7X256/128 Errata - Rev. A
Section 41.2.2 “Controller Area Network (CAN)” on page
Section 41.2.10.1 ”USART: CTS in Hardware
Section 41.2.10.3 “USART: RXBRK Flag Error in Asynchronous Mode” on page
Section 41.2.10.4 “USART: DCD is Active High instead of Low.” on page
Section 41.2.1 “Analog-to-Digital Converter (ADC)” on page
Section 41.2.7.6 “SPI: Bad Serial Clock Generation on 2nd Chip Select” on page
“AT91SAM7X512 Errata - Rev. A
Section 41.3.2 “Controller Area Network (CAN)” on page
Section 41.3.11.1 ”USART: CTS in Hardware
Section 41.3.11.3 “USART: RXBRK Flag Error in Asynchronous Mode” on page
Section 41.3.11.4 “USART: DCD is Active High instead of Low.” on page
Section 41.3.1 “Analog-to-Digital Converter (ADC)” on page
Section 41.3.8.6 “SPI: Bad Serial Clock Generation on 2nd Chip Select” on page
Characteristics”, reference to Data Converter Terminology added below table.
Characteristics”, removed reference to Tj
Characteristics”, INL and DN updated and Absolute accuracy added to
Characteristics”, added schematic in footnote to C
Parts”:
JESD97 Classification changed to e3.
Characteristics”, added t
Parts”:
622, added figure.
AT91SAM7X512/256/128 Preliminary
Handshaking”, updated.
Handshaking”, updated.
Modes”; Active mode consumption values updated. Footnote
644, added
652, added
CLCH
642, added
650, added
and t
CHCL
649, added.
658, added
to table, t
L
and C
649, added.
658, added
647, added
655, added
CHXIN
LEXT
and t
Table 38-18,
symbols.
CLXIN
updated.
Change
Request
Ref.
4596/
4597
4007
3866
3967
4659
4968
4648
3956
4645
4750
4648
3956
4645
4750
673