AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 660

• Manufacturer Part Number: AT91SAM7X128-CU
• Description: MCU ARM 128K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

41.4.1.7
41.4.1.8
41.4.1.9
41.4.1.10
41.4.1.11
660
AT91SAM7X512/256/128 Preliminary
ADC: GOVRE Bit is not Set when Disabling a Channel
ADC: OVRE Flag Behavior
ADC: EOC Set although Channel Disabled
ADC: Spurious Clear of EOC Flag
ADC: Sleep Mode
GOVRE should be set but is not.
None
When disabling channel "y" at the same instant as an end of conversion on channel "x", EOC[x]
and DRDY being already active, GOVRE does not rise.
Note:
None
When the OVRE flag (on channel i) has been set but the related EOC status (of channel i) has
been cleared (by a read of CDRi or LCDR), reading the Status register at the same instant as an
end of conversion (causing the set of EOC status on channel i), does not lead to a reset of the
OVRE flag (on channel i) as expected.
None
If a channel is disabled while a conversion is running and if a read of CDR is performed at the
same time as an end of conversion of any channel occurs, the EOC of the channel with the con-
version running may rise (whereas it has been disabled).
Do not take into account the EOC of a disabled channel
If "x" and "y" are two successively converted channels and "z" is yet another enabled channel
("z" being neither "x" nor "y"), reading CDR on channel "z" at the same instant as an end of con-
version on channel "y" automatically clears EOC[x] instead of EOC[z].
None.
If Sleep mode is activated while there is no activity (no conversion is being performed), it will
take effect only after a conversion occurs.
To activate sleep mode as soon as possible, it is recommended to write successively, ADC
Mode Register (SLEEP) then ADC Control Register (START bit field); to start an analog-to-digi-
tal conversion, in order put ADC into sleep mode at the end of this conversion.
• EOC[x] already active,
• DRDY already active,
• GOVRE inactive,
• previous data stored in LCDR being neither data from channel "y", nor data from channel "x".
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround:
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
OVRE[x] rises as expected.
6120H–ATARM–17-Feb-09