AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 299

no-image

AT91SAM7X128-CU

Manufacturer Part Number
AT91SAM7X128-CU
Description
MCU ARM 128K HS FLASH 100-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91SAM7X128-CU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7X128-CU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7X128-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT91SAM7X128-CU-999
Manufacturer:
Atmel
Quantity:
10 000
29.6.5
Register Name:
Access Type:
• TXCOMP: Transmission Completed
0 = During the length of the current frame.
1 = When both holding and shift registers are empty and STOP condition has been sent, or when MSEN is set (enable
TWI).
• RXRDY: Receive Holding Register Ready
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
• TXRDY: Transmit Holding Register Ready
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the
same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
• NACK: Not Acknowledged
0 = Each data byte has been correctly received by the far-end side TWI slave component.
1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.
6120H–ATARM–17-Feb-09
31
23
15
7
TWI Status Register
30
22
14
TWI_SR
Read-only
6
29
21
13
5
AT91SAM7X512/256/128 Preliminary
28
20
12
4
27
19
11
3
TXRDY
26
18
10
2
RXRDY
25
17
9
1
TXCOMP
NACK
24
16
8
0
299

Related parts for AT91SAM7X128-CU