AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 458

• Manufacturer Part Number: AT91SAM7X128-CU
• Description: MCU ARM 128K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

34.5.2.3
Figure 34-9. Data OUT Transfer for Non Ping-pong Endpoints
458
RX_DATA_BK0
(UDP_CSRx)
USB Bus
Packets
FIFO (DPR)
Content
Data OUT Transaction Without Ping-pong Attributes
Using Endpoints With Ping-pong Attributes
AT91SAM7X512/256/128 Preliminary
Data OUT Transaction
Data OUT
PID
Host Sends Data Payload
Written by USB Device
Data OUT 1
Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and con-
duct the transfer of data from the host to the device. Data OUT transactions in isochronous
transfers must be done using endpoints with ping-pong attributes.
To perform a Data OUT transaction, using a non ping-pong endpoint:
An interrupt is pending while the flag RX_DATA_BK0 is set. Memory transfer between the USB
device, the FIFO and microcontroller memory can not be done after RX_DATA_BK0 has been
cleared. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the
current Data OUT packet in the FIFO.
During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be
able to guarantee a constant bandwidth, the microcontroller must read the previous data pay-
load sent by the host, while the current data payload is received by the USB device. Thus two
Data OUT 1
1. The host generates a Data OUT packet.
2. This packet is received by the USB device endpoint. While the FIFO associated to this
3. The microcontroller is notified that the USB device has received a data payload polling
4. The number of bytes available in the FIFO is made available by reading RXBYTECNT
5. The microcontroller carries out data received from the endpoint’s memory to its mem-
6. The microcontroller notifies the USB device that it has finished the transfer by clearing
7. A new Data OUT packet can be accepted by the USB device.
endpoint is being used by the microcontroller, a NAK PID is returned to the host. Once
the FIFO is available, data are written to the FIFO by the USB device and an ACK is
automatically carried out to the host.
RX_DATA_BK0 in the endpoint’s UDP_ CSRx register. An interrupt is pending for this
endpoint while RX_DATA_BK0 is set.
in the endpoint’s UDP_ CSRx register.
ory. Data received is available by reading the endpoint’s UDP_ FDRx register.
RX_DATA_BK0 in the endpoint’s UDP_ CSRx register.
Set by USB Device
ACK
Host Sends the Next Data Payload
Microcontroller Read
PID
Microcontroller Transfers Data
Data OUT 1
Data OUT2
Interrupt Pending
PID
Data OUT2
NAK
PID
Cleared by Firmware,
Data Payload Written in FIFO
Data OUT
PID
Host Resends the Next Data Payload
Written by USB Device
Data OUT 2
Data OUT2
6120H–ATARM–17-Feb-09
ACK
PID