AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 672

• Manufacturer Part Number: AT91SAM7X128-CU
• Description: MCU ARM 128K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

672
Version
6120G
(Continued) Comments
AT91SAM7X512/256/128 Preliminary
SSC,
Section 31.6.5.1 ”Frame Sync
Section 31.6.6.1 ”Compare
TC,
Figure 32-2,”Clock Chaining
Section 32.6 ”Timer Counter (TC) User Interface”
405
Section 32.6.3 on page 408
Section 32.6.4 ”TC Channel Mode Register: Capture Mode”
TWI,
“Two-wire Interface
Important changes to this datasheet include a clarification of Atmel TWI compatibility with I
UDP,
Table 34-2, “USB Communication
In the USB_CSR register, the control endpoints are not effected by the bit field,
Disable” on page 475
Updated: write 1 =.... in
Updated: write 0 = ....in
Section 34.6.10 “UDP Endpoint Control and Status Register” on page
instructions regarding USB clock and system clock cycle, and updated “note” appearing under the code.
“wait 3 USB clock cycles and 3 system clock cycles before accessing DPR from RX_DATAx and TXPKTRDY bit
fields, ditto for RX_DATAx and TXPKTRDY bit field descriptions.”
Section 34.2 ”Block
domain, UDPCK specified as 48 MHz clock used by 12 MHz domain, in peripheral clock requirements.
Section 34.6 ”USB Device Port (UDP) User
Section 34.6.6 ”UDP Interrupt Mask Register”
USART,
“CLKO: Clock Output Select” on page
“USCLKS: Clock Selection” on page
Section 30.5.1 ”I/O
“TXEMPTY: Transmitter Empty” on page
Section 30.6.2 ”Receiver and Transmitter
RSTTX in US_CR register) updated by replacing 2nd sentence.
Section 30.6.5 ”IrDA
Section 30.2 ”Block
and register offsets indexed.
Lines”, 2nd and 3rd paragraphsupdated.
(TWI)”, section has been updated.
Diagram”, in the text below the block diagram, MCK specified as clock used by Master Clock
Diagram”, signal directions from pads to PIO updated in the block diagram.
Mode”, updated with instruction to receive IrDA signals.
“RX_DATA_BK0: Receive Data Bank 0”
“TXPKTRDY: Transmit Packet Ready”
Functions”, updated with max FSLEN length.
to
Selection”, added to
Data”, defined max Frame Sync Data length.
Section 32.6.13 on page
Flow”, Supported Endpoint column updated.
335, bit field in US_MR register, DIV= 8 in Selected Clock column.
337, bit field in US_MR register, typo fixed in bit field description.
342, no characters when at 1 updated.
Control”, In the fourth paragraph, Software reset effects (RSTRX and
Interface”, The register mapping table has been updated
Bit 12 of has been defined as BIT12 and cannot be masked.
Section 32.5 ”Functional
Register mapping tables consolidated in
422, register names updated with indexed offset.
bit field 15 and WAVE bit field description updated.
bit field of USB_CSR register.
bit field of USB_CSR register.
478, update to code and added
Description”.
“EPEDS: Endpoint Enable
2
Table 32-4 on page
C Standard.
6120H–ATARM–17-Feb-09
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