AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 126

• Manufacturer Part Number: AT91SAM7X128-CU
• Description: MCU ARM 128K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.2.5.6
20.2.5.7
20.2.5.8
126
AT91SAM7X512/256/128 Preliminary
Flash Security Bit Command
AT91SAM7X512 Select EFC Command
Memory Write Command
A security bit can be set using the Set Security Bit command (SSE). Once the security bit is
active, the Fast Flash programming is disabled. No other command can be run. An event on the
Erase pin can erase the security bit once the contents of the Flash have been erased.
The AT91SAM7X512 security bit is controlled by the EFC0. To use the Set Security Bit com-
mand, the EFC0 must be selected using the Select EFC command
Table 20-14. Set Security Bit Command
Once the security bit is set, it is not possible to access FFPI. The only way to erase the security
bit is to erase the Flash.
In order to erase the Flash, the user must perform the following:
Then it is possible to return to FFPI mode and check that Flash is erased.
The commands WPx, EA, xLB, xFB are executed using the current EFC controller. The default
EFC controller is EFC0. The Select EFC command (SEFC) allows selection of the current EFC
controller.
Table 20-15. Select EFC Command
This command is used to perform a write access to any memory location.
The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking
can be chained; an internal address buffer is automatically increased.
Table 20-16. Write Command
Step
1
2
Step
1
2
Step
1
2
3
4
5
• Power-off the chip
• Power-on the chip with TST = 0
• Assert Erase during a period of more than 220 ms
• Power-off the chip
Handshake Sequence
Write handshaking
Write handshaking
Handshake Sequence
Write handshaking
Write handshaking
Handshake Sequence
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Write handshaking
MODE[3:0]
CMDE
ADDR0
ADDR1
DATA
DATA
MODE[3:0]
CMDE
DATA
MODE[3:0]
CMDE
DATA
DATA[15:0]
WRAM
Memory Address LSB
Memory Address
*Memory Address++
*Memory Address++
DATA[15:0]
SEFC
0 = Select EFC0
1 = Select EFC1
DATA[15:0]
SSE
0
6120H–ATARM–17-Feb-09