AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 273

• Manufacturer Part Number: AT91SAM7X128-CU
• Description: MCU ARM 128K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

28.7.5
Name:
Access Type:
• RDRF: Receive Data Register Full
0 = No data has been received since the last read of SPI_RDR
1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read
of SPI_RDR.
• TDRE: Transmit Data Register Empty
0 = Data has been written to SPI_TDR and not yet transferred to the serializer.
1 = The last data written in the Transmit Data Register has been transferred to the serializer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
• MODF: Mode Fault Error
0 = No Mode Fault has been detected since the last read of SPI_SR.
1 = A Mode Fault occurred since the last read of the SPI_SR.
• OVRES: Overrun Error Status
0 = No overrun has been detected since the last read of SPI_SR.
1 = An overrun has occurred since the last read of SPI_SR.
An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.
• ENDRX: End of RX buffer
0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR
1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR
• ENDTX: End of TX buffer
0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR
1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR
• RXBUFF: RX Buffer Full
0 = SPI_RCR
1 = Both SPI_RCR
6120H–ATARM–17-Feb-09
TXBUFE
31
23
15
–
–
–
7
SPI Status Register
(1)
or SPI_RNCR
RXBUFF
(1)
and SPI_RNCR
SPI_SR
Read-only
30
22
14
–
–
–
6
(1)
has a value other than 0.
ENDTX
29
21
13
(1)
–
–
–
5
have a value of 0.
ENDRX
AT91SAM7X512/256/128 Preliminary
28
20
12
–
–
–
4
OVRES
27
19
11
–
–
–
3
MODF
(1)
(1)
26
18
10
–
–
–
2
or SPI_RNCR
or SPI_TNCR
(1)
(1)
or SPI_RNCR
or SPI_TNCR
TXEMPTY
TDRE
(1)
(1)
25
17
–
–
9
1
.
.
(1)
(1)
.
.
SPIENS
NSSR
RDRF
24
16
–
8
0
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