AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 61

• Manufacturer Part Number: AT91SAM7X128-CU
• Description: MCU ARM 128K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.2.4.2
Figure 13-5. User Reset State
6120H–ATARM–17-Feb-09
periph_nreset
proc_nreset
User Reset
(nrst_out)
RSTTYP
NRST
SLCK
NRST
MCK
The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in
RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behav-
ior of the system.
The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset
and the Peripheral Reset are asserted.
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a three-
cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.
When the processor reset signal is released, the RSTTYP field of the Status Register
(RSTC_SR) is loaded with the value 0x4, indicating a User Reset.
T h e
EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How-
ever, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low
externally, the internal reset lines remain asserted until NRST actually rises.
Resynch.
2 cycles
Any
Freq.
Any
N R S T
>= EXTERNAL RESET LENGTH
M a n a g e r
AT91SAM7X512/256/128 Preliminary
g u a r a n t e e s
Resynch.
2 cycles
XXX
t h a t
Processor Startup
t h e
= 3 cycles
N R S T
l i n e
0x4 = User Reset
i s
a s s e r t e d
f o r
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