M29W640GB60ZA6E NUMONYX, M29W640GB60ZA6E Datasheet - Page 24

• Manufacturer Part Number: M29W640GB60ZA6E
• Description: Flash Mem Parallel 3V/3.3V 64M-Bit 8M x 8/4M x 16 60ns 48-Pin TFBGA Tray
• Manufacturer: NUMONYX

Specifications of M29W640GB60ZA6E

• Package: 48TFBGA
• Cell Type: NOR
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Bottom
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 127
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

4.1.3
4.1.4
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Read CFI Query command
The Read CFI Query command is used to read data from the common flash interface (CFI)
memory area. This command is valid when the device is in the read array mode, or when
the device is in autoselected mode.
One bus write cycle is required to issue the Read CFI Query command. Once the command
is issued subsequent bus read operations read from the common flash interface memory
area.
The Read/Reset command must be issued to return the device to the previous mode (the
read array mode or autoselected mode). A second Read/Reset command would be needed
if the device is to be put in the read array mode from auto selected mode.
See
on the information contained in the common flash interface (CFI) memory area.
Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six bus write operations are
required to issue the Chip Erase command and start the program/erase controller.
If any blocks are protected then these are ignored and all the other blocks are erased. If all
of the blocks are protected the chip erase operation appears to start but will terminate within
about 100 μs, leaving the data unchanged. No error condition is given when protected
blocks are ignored.
During the erase operation the memory will ignore all commands, including the Erase
Suspend command. It is not possible to issue any command to abort the operation. Typical
chip erase times are given in
read operations during the chip erase operation will output the status register on the Data
Inputs/Outputs. See the section on the status register for more details.
After the chip erase operation has completed the memory will return to the read mode,
unless an error has occurred. When an error occurs the memory will continue to output the
status register. A Read/Reset command must be issued to reset the error condition and
return to read mode.
The Chip Erase command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.
Refer to
AC waveforms.
Appendix B: Common flash interface
Figure 8: Chip/block erase waveforms (8-bit mode)
Table 12: Program, erase times and endurance
(CFI), Tables 31, 32, 33, 34,
for a description of Chip Erase
35
and
cycles. All bus
36
for details