M29W640GB60ZA6E NUMONYX, M29W640GB60ZA6E Datasheet - Page 29

• Manufacturer Part Number: M29W640GB60ZA6E
• Description: Flash Mem Parallel 3V/3.3V 64M-Bit 8M x 8/4M x 16 60ns 48-Pin TFBGA Tray
• Manufacturer: NUMONYX

Specifications of M29W640GB60ZA6E

• Package: 48TFBGA
• Cell Type: NOR
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Bottom
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 127
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

4.2.3
4.2.4
Note:
Octuple Byte Program command
This is used to write eight adjacent bytes, in x8 mode, simultaneously. The addresses of the
eight bytes must differ only in A1, A0 and DQ15A-1.
12 V must be applied to the V
Program command. Care must be taken because applying a 12 V voltage to the V
will temporarily unprotect any protected block.
Nine bus write cycles are necessary to issue the command:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Double Word Program command
The Double Word Program command is used to write a page of two adjacent words in
parallel. The two words must differ only for the address A0.
Three bus write cycles are necessary to issue the Double Word Program command:
After the program operation has completed the memory will return to the read mode, unless
an error has occurred. When an error occurs bus read operations will continue to output the
status register. A Read/Reset command must be issued to reset the error condition and
return to read mode.
Note that the fast program commands cannot change a bit set to ’0’ back to ’1’. One of the
erase commands must be used to set all the bits in a block or in the whole memory from ’0’
to ’1’.
Typical program times are given in
It is not necessary to raise V
The first bus cycle sets up the command.
The second bus cycle latches the address and the data of the first byte to be written
The third bus cycle latches the address and the data of the second byte to be written
The fourth bus cycle latches the address and the data of the third byte to be written
The fifth bus cycle latches the address and the data of the fourth byte to be written
The sixth bus cycle latches the address and the data of the fifth byte to be written
The seventh bus cycle latches the address and the data of the sixth byte to be written
The eighth bus cycle latches the address and the data of the seventh byte to be written
The ninth bus cycle latches the address and the data of the eighth byte to be written
and starts the program/erase controller.
The first bus cycle sets up the Double Word Program command
The second bus cycle latches the address and the data of the first word to be written
The third bus cycle latches the address and the data of the second word to be written
and starts the program/erase controller.
PP
PP
/WP to 12 V before issuing this command.
/Write Protect pin, V
Table 12: Program, erase times and endurance
PP
/WP, prior to issuing an Octuple Byte
PP
cycles.
/WP pin
29/90