M29W640GB60ZA6E NUMONYX, M29W640GB60ZA6E Datasheet - Page 28

• Manufacturer Part Number: M29W640GB60ZA6E
• Description: Flash Mem Parallel 3V/3.3V 64M-Bit 8M x 8/4M x 16 60ns 48-Pin TFBGA Tray
• Manufacturer: NUMONYX

Specifications of M29W640GB60ZA6E

• Package: 48TFBGA
• Cell Type: NOR
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Bottom
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 127
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

4.2
4.2.1
Note:
4.2.2
Note:
28/90
Fast program commands
There are five fast program commands available to improve the programming throughput,
by writing several adjacent words or bytes in parallel:
Fast program commands can be suspended and then resumed by issuing a Program
Suspend command and a Program Resume command, respectively (see
Program Suspend command
Double Byte Program command
The Double Byte Program command is used to write a page of two adjacent bytes in
parallel. The two bytes must differ only in DQ15A-1. Three bus write cycles are necessary to
issue the Double Byte Program command:
1.
2.
3.
It is not necessary to raise V
Quadruple Byte Program command
The Quadruple Byte Program command is used to write a page of four adjacent bytes in
parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles
are necessary to issue the Quadruple Byte Program command:
1.
2.
3.
4.
5.
It is not necessary to raise V
Quadruple and Octuple Byte Program, available for x8 operations
Double and Quadruple Word Program, available for x16 operations
Write to Buffer and Program
The first bus cycle sets up the Double Byte Program command
The second bus cycle latches the Address and the Data of the first byte to be written
The third bus cycle latches the address and the data of the second byte to be written.
The first bus cycle sets up the Quadruple Byte Program command
The second bus cycle latches the address and the data of the first byte to be written
The third bus cycle latches the address and the data of the second byte to be written
The fourth bus cycle latches the address and the data of the third byte to be written
The fifth bus cycle latches the address and the data of the fourth byte to be written and
starts the program/erase controller.
PP
PP
and
/WP to 12 V before issuing this command.
/WP to 12 V before issuing this command.
Section 4.1.9: Program Resume
command).
Section 4.1.8: