M29W640GB60ZA6E NUMONYX, M29W640GB60ZA6E Datasheet - Page 31

• Manufacturer Part Number: M29W640GB60ZA6E
• Description: Flash Mem Parallel 3V/3.3V 64M-Bit 8M x 8/4M x 16 60ns 48-Pin TFBGA Tray
• Manufacturer: NUMONYX

Specifications of M29W640GB60ZA6E

• Package: 48TFBGA
• Cell Type: NOR
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Bottom
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 127
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

4.2.8
4.2.9
Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to read/reset mode from unlock
bypass mode. Two bus write operations are required to issue the Unlock Bypass Reset
command. Read/Reset command does not exit from unlock bypass mode.
Write to Buffer and Program command
The Write to Buffer and Program command makes use of the device’s 32-byte write buffer to
speed up programming. 16 words/32 bytes can be loaded into the write buffer. Each write
buffer has the same A4-A22 addresses.The Write to Buffer and Program command
dramatically reduces system programming time compared to the standard non-buffered
Program command.
When issuing a Write to Buffer and Program command, the V
High, V
See
Five successive steps are required to issue the Write to Buffer and Program command:
1.
2.
3.
4.
5.
All the addresses used in the Write to Buffer and Program operation must lie within the
same page. If an address is written several times during a Write to Buffer and Program
operation, the address/data counter will be decremented at each data load operation and
the data will be programmed to the last word loaded into the buffer. Invalid address
combinations or failing to follow the correct sequence of bus write cycles will abort the Write
to Buffer and Program.
The status register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status
during a Write to Buffer and Program operation. It is possible to detect program operation
fails when changing programmed data from ‘0’ to ‘1’, that is when reprogramming data in a
portion of memory already programmed. The resulting data will be the logical OR between
the previous value and the current value.
To program the content of the write buffer, this command must be followed by a Write to
Buffer and Program Confirm command.
A Write to Buffer and Program Abort and Reset command must be issued to abort the Write
to Buffer and Program operation and reset the device in read mode.
Table 12
The Write to Buffer and Program command starts with two unlock cycles
The third bus write cycle sets up the Write to Buffer and Program command. The setup
code can be addressed to any location within the targeted block.
The fourth bus write cycle sets up the number of words to be programmed. Value n is
written to the same block address, where n+1 is the number of words to be
programmed. n+1 must not exceed the size of the write buffer or the operation will
abort
The fifth cycle loads the first address and data to be programmed
Use n bus write cycles to load the address and data for each word into the write buffer.
Addresses must lie within the range from the start address+1 to the start address + n-1.
Optimum performance is obtained when the start address corresponds to a 64-byte
boundary. If the start address is not aligned to a 64-byte boundary, the total
programming time is doubled.
IH
or raised to V
for details on typical Write to Buffer and Program times in both cases.
PPH
.
PP/
WP pin can be either held
31/90