r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1006

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)

frame (single-frame/multi-buffer). As an example of single-frame/multi-buffer operation, the data

portion that is used in a fixed manner in each Ethernet frame transmission can be referenced by

multiple descriptors. For example, multiple descriptors can share the destination address and

transmit source address in an Ethernet frame, and the remaining data can be stored in each

separate buffer.

Before the TR bits in EDTRR are set to 11, the user sets whether the bits of the descriptor are

valid or invalid bit and sets other descriptor configuration. After Ethernet frame transmission, the

E-DMAC disables the valid/invalid bits of the descriptor and writes status information. This

operation is referred to as write-back.

When using TD0, the user should write desired values to bits 31 to 28 and 26 according to the

descriptor configuration. Bits 27 and 25 to 0 should be cleared to 0.

Rev. 1.00 Oct. 01, 2007 Page 940 of 1956

REJ09B0256-0100

Note: *According to the descripotr lenght set by the DL0 and DL 1 bits in EDMR, the padding size is detemined as follows:

Transmit Descriptor 0 (TD0)

For 16 bytes Padding = 4 bytes

For 32 bytes padding = 20bytes

For 64 bytes Padding = 52bytes

Figure 23.3 Relationship between Transmit Descriptor and Transmit Buffer

Transmit deschriptor

Padding (4/20/52 bytes)*

Transmit buffer

Valid transmit data