r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1012

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)

frame can be stored in buffer 1 (set RBL to 14 bytes) and the remaining data can be stored in

buffer 2 (set RBL to 1500 bytes). All receive frames, of course, can be stored in a single buffer if

multiple descriptors are prepared and RBL of each descriptor is set to more than 1514 bytes

(maximum Ethernet frame length).

The user sets whether the bits of the descriptor are valid or invalid and whether the descriptor

represents the end of the descriptor list in RD0 before the RR bit in EDRRR is set to 1 and the

start of a read by the E-DMAC. After receive DMA transfer of an Ethernet frame by the E-

DMAC, the E-DMAC disables the valid/invalid bits of the descriptor and writes status

information. This operation is referred to as write-back.

When using RD0, the user should write desired values to bits 31 and 30 according to the

descriptor configuration. Bits 29 to 0 should be cleared to 0.

Rev. 1.00 Oct. 01, 2007 Page 946 of 1956

REJ09B0256-0100

Note: *According to the descripotr lenght set by the DL0 and DL 1 bits in EDMR, the padding size is detemined as follows:

Receive Descriptor 0 (RD0)

For 16 bytes Padding = 4 bytes

For 32 bytes padding = 20bytes

For 64 bytes Padding = 52bytes

Figure 23.4 Relationship between Receive Descriptor and Receive Buffer

Receive deschriptor

Padding (4/20/52 bytes)*

Transmit buffer

Valid transmit data