r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 442

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 11 Local Bus State Controller (LBSC)
When the first half area is accessed, bits IW[3:0] in CSnWCR (n=5 or 6) and bits PCWA[1:0],
TEDA[2:0], and TEHA[2:0] in CSnPCR (n=5 or 6) are selected. When the second half area is
accessed, bits IW[3:0] in CSnWCR (n=5 or 6) and bits PCWB[1:0], TEDB[2:0], and TEHB[2:0]
in CSnPCR (n=5 or 6) are selected.
Bits PCWA[1:0] and PCWB[1:0] can be used to set the number of wait cycles to be inserted in a
low-speed bus cycle as 0, 15, 30, or 50. This value is added to the number of inserted wait cycles
specified by IW bit in CSnWCR or PCIW bit in CSnPCR. Bits PEDA[2:0] and PEDB[2:0] (with a
setting range from 0 to 15) can be used to ensure the setup times of the address, CSn, CE2A,
CE2B, and PCC_REG to the RD and WE1 signals. Bits TEHA[2:0] and TEHB[2:0] (with a
setting range from 0 to15) can be used to ensure the hold times of the address, CSn, CE2A, CE2B,
and PCC_REG REG to the RD and WE1 signals.
Bits IW[3:0] in the CS5 bus control register (CS5BCR) or CS6 bus control register (CS6BCR) are
used to set the number of idle cycles between cycles. The selected number of wait cycles between
cycles depends only on the area to be accessed (area 5 or 6). When area 5 is accessed, bits IW[3:0]
in CS5WCR are selected, and when area 6 is accessed, bits IW[3:0] in CS6WCR are selected.
In 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed in wrap around method according to the set bus width. The bus is not
released during this transfer.
ATA complement mode is to access the ATA device register that connected to this LSI. Device
Control Register, Alternate Status Register, Data Register, and Data Port can be accessed in ATA
complement mode.
To access Device Control Register and Alternate Status Register, PIO byte access is used, and to
access Data Register, PIO word access is used. When PIO byte access is executed, CE1x is
negated and CE2x is asserted. When PIO word access is executed, CE1x is asserted and CE2x is
negated.
To access Data Port is used DMA transfer. Then DMAC must be set burst mode, level detection,
overrun 0, DACK output to the correspondent PCMCIA connected area, and set to 1
DACKBST[2:0] bit in BCR of correspondent DMA transfer channels. When DMA transfer of
ATA complement mode area is executed, both CE1x and CE2x are not asserted.
And set to 1 the DACKBST bit in BCR of correspondent DMA transfer channel, then the
correspondent DACK signal is being asserted from the first to the end of the DMA transfer cycle.
Rev. 1.00 Oct. 01, 2007 Page 376 of 1956
REJ09B0256-0100