r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 562

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 13 PCI Controller (PCIC)
Rev. 1.00 Oct. 01, 2007 Page 496 of 1956
REJ09B0256-0100
Bit
4
3
2
Bit Name
PEDITR
TADIM
MADIM
Initial
Value
0
0
0
R/W
SH: R/WC
PCI: R
SH: R/WC
PCI: R
SH: R/WC
PCI: R
Description
Data Parity Error Interrupt for Target PERR
Indicates that the PERR signal has been received
during a target read access (only detected when
PCICMD.PER is set to 1) when the PCIC functions
as a target.
0: PERR detection interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: PERR detection interrupt occurs
[Set condition]
When a PERR detection interrupt occurs.
Target-Abort Detection Interrupt for Master
When the PCIC functions as a master, it has
detected a target-abort, that is, the transaction is
terminated.
0: Target-abort interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Target-abort interrupt occurs
[Set condition]
When a target-abort interrupt occurs.
Master-Abort Interrupt for Master
Indicates that the PCIC has terminated a transaction
with a master-abort when the PCIC functions as a
master.
0: Master-abort interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Master-abort interrupt occurs
[Set condition]
When a master-abort interrupt occurs.